<--- Back to Details
First PageDocument Content
Electronic engineering / High-definition television / High Efficiency Video Coding / H.264/MPEG-4 AVC / Video compression picture types / Deblocking filter / Context-adaptive binary arithmetic coding / Speedup / Parallel computing / Video compression / Video / Videotelephony
Date: 2012-01-24 08:30:03
Electronic engineering
High-definition television
High Efficiency Video Coding
H.264/MPEG-4 AVC
Video compression picture types
Deblocking filter
Context-adaptive binary arithmetic coding
Speedup
Parallel computing
Video compression
Video
Videotelephony

PARALLEL VIDEO DECODING IN THE EMERGING HEVC STANDARD Mauricio Alvarez-Mesa1,2 , Chi Ching Chi1 , Ben Juurlink1 , Valeri George2 , Thomas Schierl2 1 Embedded Systems Architectures, Technische Universit¨at Berlin, Berlin

Add to Reading List

Source URL: iphome.hhi.de

Download Document from Source Website

File Size: 267,95 KB

Share Document on Facebook

Similar Documents

J Real-Time Image Proc:571–587 DOIs11554y ORIGINAL RESEARCH PAPER  Exploiting task and data parallelism for advanced video coding

J Real-Time Image Proc:571–587 DOIs11554y ORIGINAL RESEARCH PAPER Exploiting task and data parallelism for advanced video coding

DocID: 1qFa3 - View Document

Professional H.265/HEVC Encoder LSI Toward High-Quality 4K/8K Broadcast Infrastructure Code Name: NARA (Next-generation encoder Architecture for Real-time HEVC Application)  Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura,

Professional H.265/HEVC Encoder LSI Toward High-Quality 4K/8K Broadcast Infrastructure Code Name: NARA (Next-generation encoder Architecture for Real-time HEVC Application) Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura,

DocID: 1qgPv - View Document

2014 IEEE International Conference on Acoustic, Speech and Signal Processing (ICASSP)  COOPERATIVE CPU+GPU DEBLOCKING FILTER PARALLELIZATION FOR HIGH PERFORMANCE HEVC VIDEO CODECS Diego F. de Souza, Nuno Roma, Leonel Sou

2014 IEEE International Conference on Acoustic, Speech and Signal Processing (ICASSP) COOPERATIVE CPU+GPU DEBLOCKING FILTER PARALLELIZATION FOR HIGH PERFORMANCE HEVC VIDEO CODECS Diego F. de Souza, Nuno Roma, Leonel Sou

DocID: 1q2AE - View Document

TOWARDS GPU HEVC INTRA DECODING: SEIZING FINE-GRAIN PARALLELISM Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa INESC-ID, IST, Universidade de Lisboa Rua Alves Redol 9, Lisboa, Portugal {diego.souza,

TOWARDS GPU HEVC INTRA DECODING: SEIZING FINE-GRAIN PARALLELISM Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa INESC-ID, IST, Universidade de Lisboa Rua Alves Redol 9, Lisboa, Portugal {diego.souza,

DocID: 1pRHt - View Document

GPU Acceleration of the HEVC Decoder Inter Prediction Module Diego F. de Souza, Aleksandar Ilic, Nuno Roma and Leonel Sousa INESC-ID, IST, Universidade de Lisboa Rua Alves Redol 9, , Lisbon, Portugal Email: {dieg

GPU Acceleration of the HEVC Decoder Inter Prediction Module Diego F. de Souza, Aleksandar Ilic, Nuno Roma and Leonel Sousa INESC-ID, IST, Universidade de Lisboa Rua Alves Redol 9, , Lisbon, Portugal Email: {dieg

DocID: 1oW64 - View Document