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Compiler optimizations / Computer memory / Programming language implementation / Compiler construction / Parallel computing / Cell / Compiler / SPMD / Software pipelining / Computing / Software engineering / Computer programming


Compilation for Explicitly Managed Memory Hierarchies Timothy J. Knight Ji Young Park Manman Ren Mike Houston
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Document Date: 2007-01-12 21:55:15

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semiconductor technology / child processor / Software prefetching / software-pipelining / static compilation solution / software-managed storage hierarchies / child processors / software-pipelining transformation / control processor / Cell processor / minimum compilation infrastructure / search problems / software-pipelining implementation / software-pipelining algorithm / graphics processors / software-pipelining loop transformations / software-managed memory hierarchies / 1900XT graphics processor / high-peak-performance processing elements / non-uniform cluster computing / on-chip / /

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University of California / National Science Foundation / Department of Energy / Stanford University / Barcelona Supercomputing Center / IEEE Computer Society / /

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Mi / D. Chase / V / C. Grothoff / V / Erez Kayvon Fatahalian Alex Aiken William / Mike Houston Mattan Erez Kayvon / L. Chamberlain / Figure / William J. Dally Pat Hanrahan / Each Exec / /

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abstract machine model / Representative operational rules / Exec. / General / hardware DMA controller / asynchronous DMA controller / programming model for the Cell BE architecture / Memory Flow Controller / programmer / /

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Cell / Cell system / Verlet / Cell processor / /

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Cell Broadband Engine processor / Broadband / graphics processors / semiconductor technology / 3.2GHz Cell processor / SPE processor / child processor / Operating Systems / Cell processor / ATI 1900XT graphics processor / software-pipelining algorithm / eight processors / Exec grouping processors / Imagine processor / child processors / control processor / PowerPC control processor / simulation / same child processors / /

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