Patel

Results: 1081



#Item
11PREPRINT:

PREPRINT: "H. Kashif, H. Patel, and S. Fischmeister, "Using Link-level Latency Analysis for Path Selection for Real-time Communication on No Cs," in proceedings of IEEE Asia and South Pacific Design Automation Conference

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Source URL: caesr.uwaterloo.ca

Language: English - Date: 2017-11-20 15:53:14
    12PREPRINT:

    PREPRINT: "H. Kashif, S. Gholamian, R. Pellizzoni, H. Patel, and S. Fischmeister, "ORTAP: An Offset-based Response Time Analysis for a Pipel ined Communication Resource Model," in proceedings of the 14th IEEE Real-Time a

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    Source URL: caesr.uwaterloo.ca

    Language: English - Date: 2017-11-20 15:53:02
      13HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores ∗ Nivedita Sritharan, Anirudh Kaushik, Mohamed Hassan, Hiren Patel November 30, 2017 This technical report provides additio

      HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores ∗ Nivedita Sritharan, Anirudh Kaushik, Mohamed Hassan, Hiren Patel November 30, 2017 This technical report provides additio

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      Source URL: caesr.uwaterloo.ca

      Language: English - Date: 2017-11-30 21:46:31
        14CAROL ZOU 1439 Brown St #1, Philadelphia, PAtel  http://thisliferecorded.com

        CAROL ZOU 1439 Brown St #1, Philadelphia, PAtel http://thisliferecorded.com

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        Source URL: thisliferecorded.com

        Language: English - Date: 2018-06-04 18:34:39
          15PREPRINT:

          PREPRINT: "M. Hassan, H. Patel, and R. Pellizzoni, "A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Syste ms," in proceedings of the IEEE Real-Time and Embedded Technology and Applicati

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          Source URL: caesr.uwaterloo.ca

          Language: English - Date: 2017-11-20 15:53:06
            16

            Buffer Space Allocation for Real-Time Priority-Aware Networks Hany Kashif and Hiren Patel Electrical and Computer Engineering

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            Source URL: caesr.uwaterloo.ca

            Language: English - Date: 2017-11-20 15:53:11
              17Center for Global Workers’ Rights (CGWR) School of Labor and Employment Relations The Pennsylvania State University 506 Keller Building, University Park, PATel: (

              Center for Global Workers’ Rights (CGWR) School of Labor and Employment Relations The Pennsylvania State University 506 Keller Building, University Park, PATel: (

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              Source URL: ler.la.psu.edu

              Language: English - Date: 2016-04-21 10:49:00
                18Reverse-engineering Embedded Memory Controllers through Latency-based Analysis Mohamed Hassan, Anirudh M. Kaushik and Hiren Patel

                Reverse-engineering Embedded Memory Controllers through Latency-based Analysis Mohamed Hassan, Anirudh M. Kaushik and Hiren Patel

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                Source URL: caesr.uwaterloo.ca

                Language: English - Date: 2017-11-20 15:53:04
                  19

                  PREPRINT: "H. Kashif, S. Gholamian, and H. Patel, "SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource M odel," IEEE Transactions on Computers, vol. 64, pp, Apr. 2015." IEEE

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                  Source URL: caesr.uwaterloo.ca

                  Language: English - Date: 2017-11-20 15:52:59
                    20Voronoi Diagrams Robust and Efficient implementation Master’s Thesis Defense Nirav Patel Binghamton University Department of Computer Science

                    Voronoi Diagrams Robust and Efficient implementation Master’s Thesis Defense Nirav Patel Binghamton University Department of Computer Science

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                    Source URL: www.cs.binghamton.edu

                    Language: English - Date: 2006-01-16 13:56:20