Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton Altera Corp. 101 Innovation Drive San Jose, CA 95134 {jpistori,mhutton - Pistorius - Document - PDFSEARCH.IO - Document Search Engine

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	Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton Altera Corp. 101 Innovation Drive San Jose, CA 95134 {jpistori,mhutton}@altera.com Add to Reading List Document Date: 2007-04-20 22:36:42 Open Document File Size: 132,80 KB Share Result on Facebook City San Jose / / Company Quartus II Software / IBM / ABC / AIG / Programmable Hardware / RTL / Altera Corp. / VLSI Systems / Mike Hutton Altera Corp. / read using QIS / / / Facility Robert Brayton EECS Department University of California Berkeley / University of Massachusetts / University of California / / IndustryTerm logic network / placement tool / power analysis tool / logic synthesis tool / technology mapping algorithms / synthesis tool / verification tools / technology progresses / technology mapping tool / synthesis tools / particular placement tool / chosen target device / placement tools / physical design tool / hierarchical network / technology nodes / target device / comparable state-of-the-art tool / industrial and academic tools / macro block inference tools / technology mapping / combinational and sequential logic networks / technology mapping tools / physical design tools / logic synthesis tools / verification tool / / MarketIndex ISPD / QUIP / / Organization University of California / University of Massachusetts / Amherst / ASIC / Robert Brayton EECS Department University / Univ. of Toronto / / Person Joachim Pistorius / Sven Kapferer / Russ Tessier / Ulrich Brüning / Robert Brayton / Ahmad Darabiha / Jonathan Rose / Lev Node / Josh Fender / Meghal Varia / Ian Milton / Lilian Atieno / David Slogsnat / Alexander Giese / Ryan Kastner / Swati Pathak / Alan Mishchenko / Sriram Swaminathan / Anup Hosangadi / / Position BLIF writer / first author / CAD tool designer / / Product RAM / Synthesis version 7.1 / Synthesis 7.1 / / ProgrammingLanguage Tcl / Verilog / / ProvinceOrState California / / Technology FPGA / RAM / CAD algorithms / 42 655 298 85 54 755 788 389 Type FIR Filter Weather Radar Encryption / technology mapping algorithms / VHDL / pdf / ASIC / Verilog / simulation / DSP / CAD / / URL http / SocialTag Logic synthesis Physical design Register-transfer level Altera Quartus Place and route Application-specific integrated circuit Integrated circuit design Digital electronics Semiconductor intellectual property core Electronic engineering