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Computing / Standard cell / Register-transfer level / Apache Ant / Tcl / Verilog / Placement / Place and route / Make / Electronic engineering / Electronic design automation / Software


Document Date: 2008-01-22 15:44:19

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File Size: 332,10 KB

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Company

RTL / Synopsys / CVS / /

Facility

µm Standard Cell Library / /

IndustryTerm

heuristic algorithms / metal layer / Place+route tools / place+route tool / search path / metal layers / /

Position

wb / Attribute Editor / /

ProgrammingLanguage

TCL / Verilog / /

PublishedMedium

the Encounter User Guide / /

Technology

Verilog / pdf / SMIPSv1 processor / GUI / Cmp / /

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