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Routing Tables: Is Smaller Really Much Better? Kevin Fall Gianluca Iannaccone Sylvia Ratnasamy P. Brighten Godfrey
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Document Date: 2009-11-18 18:31:22

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City

Seattle / /

Company

Cisco / Wiley-IEEE Press / Australian Telecommunication Networks / Intel / Juniper Networks / /

Currency

pence / USD / /

Facility

Kevin Fall Gianluca Iannaccone Sylvia Ratnasamy P. Brighten Godfrey University of Illinois / /

IndustryTerm

required base processing throughput / times more memory chips / data plane processing / memory products / exotic devices / shortest path algorithm / Internet routers / longest matching prefix algorithm / physical network media / maximum per-router update processing time1 / mean processing time / 3GHz processor / basic router / hard real-time performance requirement / exotic technology / route processing algorithm / fundamental processing limitation / Internet topology / update processing time / default-free zone routers / control plane route processing / data structures commercial routers / control network / purpose processors / bank / aggregation service router / packet processing workloads / purpose processor systems / Internet Protocol / per-router update processing time / Internet routing / base processing time / manufacturing / computing / route processor / low latency applications / route processors / memory chips / packet processing time / model router / /

Organization

ASIC / University of Illinois / /

Person

Z. Dittia / Scott Shenker / Hari Balakrishnan / Daekyeong Moon / Teemu Koponen / H. Jonathan Chao / David G. Andersen / Will Eatherton / Zubin Dittia / Nick Feamster / Geoff Huston / Grenville Armitage / George Varghese / /

Position

network designer / RV collector / representative / /

ProvinceOrState

Illinois / Washington / /

Technology

IPv6 / ASR1004 aggregation service router / control network / Internet routers / route processing algorithm / two 576 Mbit chips / shortest path algorithm / cache memory / BGP router / Random Access / SRAM / Benchmarking BGP routers / html / Accountable Internet Protocol / 2.66GHz processor / memory chips / CRS-1 router / integrated circuits / route processor / pdf / 576 Mbit/chip / 3620 router / ASIC / default-free zone routers / longest matching prefix algorithm / route processors / load balancing / building routers / Tree-BitMap algorithm / basic router / model router / purpose processors / component technologies / http / tested processors / IPv4 / simulation / DRAM chips / 3GHz processor / LPM algorithm / 5 memory chips / /

URL

www.juniper.net/techpubs/software/erx / http /

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