| Document Date: 2013-03-04 06:05:03
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Company Xilinx Inc. / New Designs Reference Design Simulation Mentor Graphics Corporation / / Facility LOCK port / IN port / / IndustryTerm synthesis tool / vary depending on synthesis tool / / NaturalFeature Fibre Channel / / Person LANE DECODE SYNC / Matt DiPaolo / Nick McKay / / / Position 64B/66B Encoder/Decoder Author / / ProgrammingLanguage E / R / DC / K / T / Verilog / / Technology FPGA / Simulation / Verilog / VHDL / Fibre Channel / Gigabit Ethernet / / URL http /
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Product Not Recommended for New Designs Application Note: Virtex-II and Virtex-II Pro Devices R