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Planning / Scheduling algorithms / Computer architecture / Scheduling / Multi-core processor / Thread / Preesm / Latency / Computer cluster / Computing / Concurrent computing / Parallel computing


Document Date: 2009-03-21 16:21:27

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City

Rennes / Detroit / /

Company

Texas Instruments / /

Country

United States / /

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Facility

University of California at Berkeley / /

IndustryTerm

list scheduling algorithm / genetic algorithm / distributed real-time executives / purpose processors / simulation tool / multi-core processors / list scheduling solution / 3GPP technical specification group radio access network / intermediate solutions / realistic systems / real-time complex signal processing algorithms / message passing systems / architecture exploration tool / refinement algorithms / signal processing algorithms / parallel processors / automatic code partitioning tool / static scheduling algorithm / /

Organization

University of California / Institut d’Electronique / /

Person

Algorithm / Jean-François Nezan / Scenario / Oliver Sinnen / /

Position

PREESM scheduler Scheduler / parallel transfer controller / editor / cores implementation IP-XACT Scheduler / DAG implementation IP-XACT Scheduler / DAG DAG Scheduler / list scheduler / DAG implementation IP-XACT heuristics Scheduler / scheduler / Scheduler module structure The PREESM scheduler / usual workflow cost Architecture editor / PREESM scheduler / /

ProgrammingLanguage

XML / ABC / /

ProvinceOrState

California / Michigan / /

Technology

DAG implementation IP-XACT heuristics Scheduler ABC cost Genetic algorithms / XML / usual workflow cost Architecture editor Algorithm / signal processing algorithms / Switchable scheduling algorithms / static scheduling algorithm / LTE RACH-PD algorithm / purpose processors / genetic algorithm / studied algorithm / list scheduling algorithm / From algorithm / simulation / refinement algorithms / 3G / half-duplex / Scheduling heuristics Three algorithms / Scheduling algorithms / PREESM list scheduling algorithm / /

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