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Computer memory / Cache / Computer architecture / Compiler optimizations / CPU cache / Central processing unit / Opteron / Cell / Sparse matrix-vector multiplication / Loop nest optimization / Multi-core processor / Advanced Micro Devices
Date: 2012-09-07 00:12:17
Computer memory
Cache
Computer architecture
Compiler optimizations
CPU cache
Central processing unit
Opteron
Cell
Sparse matrix-vector multiplication
Loop nest optimization
Multi-core processor
Advanced Micro Devices

Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc

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