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Date: 2012-09-06 23:48:36Computer architecture Computing Computer hardware Computer memory Opteron Cell Multi-core processor Intel Core SPARC T5 Advanced Micro Devices Xeon CPU cache | Optimization of a Lattice Boltzmann Computation on State-of-the-Art Multicore Platforms Samuel Williams∗,a,b , Jonathan Cartera , Leonid Olikera , John Shalfa , Katherine Yelicka,b a CRD/NERSC, b CSAdd to Reading ListSource URL: crd.lbl.govDownload Document from Source WebsiteFile Size: 1,07 MBShare Document on Facebook |
Power-aware Computing: Measurement, Control, and Performance Analysis for Intel Xeon Phi Azzam Haidar∗ , Heike Jagode∗ , Asim YarKhan∗ , Phil Vaccaro∗ , Stanimire Tomov∗ , Jack Dongarra∗†‡ {haidar|jagode|DocID: 1vr39 - View Document | |
Performance and Tuning Considerations for SAS on the Intel Xeon E5 v4 Series Processors and the Vexata VX-100F Storage SystemDocID: 1v2yr - View Document | |
iWARP Support in Scalable Xeon PlatformDocID: 1v0fP - View Document | |
Cotización PLAN XEON E3-2 PERIODO Valor Neto Mensual IVA (19%)DocID: 1uVmN - View Document | |
AMBER: The How, What and Why on an Intel® Xeon Phi™ Perri Needham & Ross Walker (SDSC / UCSD)DocID: 1uONM - View Document |