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Electronic design / Integrated circuits / MOSFET / CMOS / Semiconductor device modeling / Process variation / Threshold voltage / Current mirror / Bipolar junction transistor / Electronic engineering / Electrical engineering / Logic families


Document Date: 2010-03-03 12:55:43

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City

Allentown / Tempe / Victoria / /

Company

Motorola Inc. / AT&T Bell Laboratories / Herman Research Laboratories / IEEE TRANSACTIONS / /

Country

Canada / Australia / /

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USD / /

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Facility

Arizona State University / University of Waterloo / Monash University / Rochester Institute of Technology / /

IndustryTerm

metal coverage effects / wider devices / technology development / nMOS device / reference device / differential pair applications / wireless applications / semiconductor device / short devices / pMOS devices / gigabit optical communication applications / technology featuring / polysilicon/metal edge grains / narrow/long devices / parallel devices / m-wide device / /

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Boron channel / /

Organization

Rochester Institute of Technology / Rochester / University of Waterloo / Monash University / Melbourne / Arizona State University / State Electricity Commission / /

Person

Patrick G. Drennan / Colin C. McAndrew / Nassif / /

Position

Director of the Enabling Technology Center / Editor / model at the same conditions / designer / comprehensive MOSFET mismatch model / /

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New York / Victoria / Pennsylvania / Arizona / /

Technology

semiconductor / ADC / 0.18- m technology / 0.13- m CMOS technology / 3-D / Integrated Circuits / RFBiCMOS technology / pdf / 0.25- m BiCMOS technology / CMOS technology / 0.25- m CMOS technology / gigabit / simulation / Digital Object Identifier / integrated circuit / /

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