![Formal methods / Altos Design Automation / Statistical static timing analysis / Static timing analysis / Timing closure / Standard cell / SPICE / Process variation / Synopsys / Electronic engineering / Electronic design automation / Software Formal methods / Altos Design Automation / Statistical static timing analysis / Static timing analysis / Timing closure / Standard cell / SPICE / Process variation / Synopsys / Electronic engineering / Electronic design automation / Software](https://www.pdfsearch.io/img/eeb09702aa808bc56ec13344ead3b334.jpg)
| Document Date: 2009-12-15 20:45:08 Open Document File Size: 223,85 KBShare Result on Facebook
City San Jose / / Company Mentor Graphics Inc. / Synopsys Inc. / Infinisim Inc. / Cadence Design Systems Inc. / / / / IndustryTerm manufacturing sign-off / smart algorithms / / OperatingSystem CentOS / Linux / / / Product OmegaSim / ADiT / / ProgrammingLanguage Tcl / / ProvinceOrState California / / Technology simulation / SRAM / system-on-chip / Linux / API / / URL www.altos-da.com / /
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