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Processor-in-memory
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21	This is the author’s version of the work. The definitive work was published in Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2009), pp Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2009-07-28 09:29:41 Parallel computing GPGPU Graphics hardware Video cards Cell Lookup table Memory barrier Multi-core processor Compiler optimization Computing Computer hardware Computer architecture
22	This is the author’s version of the work. The definitive work was published in Proceedings of the SPIE: Medical Imaging 2011: Image Processing, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. Detector Defect Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2011-01-15 11:56:21 Video cards Nvidia Parallel computing GPGPU CUDA Thread Nvidia Quadro Memory barrier Multi-core processor Computing Concurrent computing Computer hardware
23	Elo All-in-One PC Screen Size Touch Technology Processor Memory Add to Reading List Source URL: www.touchscreen.com.hk Language: English - Date: 2014-08-11 05:20:51 Power Mac G5 IPod Touch Nvidia Ion Dell Inspiron Sony VAIO P series Computing Apple Inc. Computer hardware
24	Theme Feature Scalable Processors in the Billion-Transistor Era: IRAM Conventional architectures will not efficiently scale a hundredfold to Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 1997-08-20 20:39:53 Computer engineering Central processing unit Parallel computing Computer memory Microprocessors The Berkeley IRAM Project Microarchitecture Superscalar Vector processor Computing Computer hardware Computer architecture
25	License Copyright © 2008 Ciaran McHale. Permission is hereby granted, free of charge, to any person obtaining a copy of this training course and associated documentation files (the “Training Course"), to deal in the T Add to Reading List Source URL: www.ciaranmchale.com Language: English - Date: 2008-05-17 08:17:25 Microprocessors Parallel computing Central processing unit Computer memory Scalability Multi-core processor CPU cache Lock Cache Computing Concurrent computing Threads
26	Writing for ALL Subjects with the IntelliKeys Promote academic learning and participation in class assignments with Overlay Maker, the IntelliKeys and a talking word-processor. About Those Current Events Teachers often a Add to Reading List Source URL: www.projectparticipate.org Language: English - Date: 2002-04-22 17:16:33 Overlay Virtual memory
27	E16G301 EPIPHANYTM 16-CORE MICROPROCESSOR Epiphany - The world leader in microprocessor energy efficiency The Epiphany is a scalable multicore architecture with up to 4,095 processors sharing a common 32 Add to Reading List Source URL: www.adapteva.com Language: English - Date: 2014-03-11 17:30:33 Motherboard Microprocessors Computer memory Direct memory access System on a chip Multi-core processor Field-programmable gate array Computer hardware Electronic engineering Computing
28	Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Xiaojun Yang, Stamatis Kavadias, Manolis Katevenis Institute of Comp Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:58 Electronic engineering Computer architecture Parallel computing Scratchpad memory CPU cache Remote direct memory access Multi-core processor Network On Chip Throughput Computing Computer memory Computer hardware
29	Reinventing Scheduling for Multicore Systems Silas Boyd-Wickizer, Robert Morris, M. Frans Kaashoek (MIT) A BSTRACT cache in other cores, but if the application stays on one Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2015-04-29 10:31:17 Microprocessors Central processing unit Computer memory Parallel computing CPU cache Multi-core processor Scheduling Thread Memory hierarchy Computing Computer hardware Computer architecture
30	Tagged memory and minion cores in the lowRISC SoC December 2014 lowRISC project team Computer Laboratory Add to Reading List Source URL: www.lowrisc.org Language: English - Date: 2015-05-13 16:22:20 Instruction set architectures Central processing unit Microprocessors Digital electronics CPU cache Pointer AMD 10h Multi-core processor ARM architecture Computer architecture Computer hardware Computing

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