| Document Date: 2013-12-20 06:36:55
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City Berlin / Amherst / / Company Strong PUF / F. Employed Computational Resources / S&P / / Country Germany / United States / / Currency EUR / / / Facility University of Massachusetts Amherst / Rice University / / IndustryTerm isochronous hardware / minuscule manufacturing irregularities / analytical solution / cryptographic protocols / machine learning algorithms / earlier algorithms / valid solution / tailormade non-linear regression algorithm / vulnerable hardware systems / software attacks / security protocols / / Organization Rice University / Houston / United Nations / University of Massachusetts Amherst / / Person Ahmed Mahmoud / Wayne Burleson / Xiaolin Xu / / Position XORs Arbiter / final XOR Arbiter / future Arbiter / k-XOR Arbiter / ETHODOLOGY A. Arbiter PUF Variants Arbiter / single Arbiter / ith Arbiter / individual Arbiter / n-bit Arbiter / XORbased Arbiter / modeling single Arbiter / basic / standard Arbiter / parallel standard Arbiter / standard Arbiter / RT / Major / parallel Arbiter / single parallel Arbiter / internal / parallel single Arbiter / =arbiter / Controller / Arbiter / so-called XOR Arbiter / XOR Arbiter / / Product Intel Xeon X5650 processor / Intel Xeon X5650 / / ProgrammingLanguage R / C / ML / / ProvinceOrState Texas / Massachusetts / / Technology Xeon X5650 processor / PUF-based security protocols / FPGA / LR algorithms / RAM / machine learning algorithms / one processor / LR algorithm / tailormade non-linear regression algorithm / polynomial ML-algorithm / cloning / secret key / machine learning / Simulation / SRAM / /
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Power and Timing Side Channels for PUFs and their Efficient Exploitation Ulrich R¨uhrmair, Xiaolin Xu, Jan S¨olter, Ahmed Mahmoud, Farinaz Koushanfar, Wayne Burleson Abstract—We discuss the first power and timing sid