| Document Date: 2012-03-17 07:08:04
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City Oxford / / Company MoM / Xputers / / IndustryTerm data sequencer hardware / typical algorithm / important algorithms / gates/chip / target technology / compound operator / computational devices / systolizable algorithm / field-programmable technology / important applications / arithmetic applications / systolizable algorithms / software kind / chosen field-programmable media / fieldprogrammable media / term interconnect-reprogrammable media / classical technology platforms / multi-chip solutions / technology platforms / cache travel step / compilation technology / narrow bandwidth device / parallel computer systems / interconnect-reprogrammable media / technology transfer / / Organization ASIC / Universität Kaiserslautern Postfach / / Person Helmut Reinig / Karin Schmidt / Wayne Luk / Michael Weber Fachbereich Informatik / Reiner W. Hartenstein / / Position author / controller / left end / / Technology semiconductor / RAM / ASIC / field-programmable technology / technology of field-programmable logic / target technology / Xputer processor / commercially important algorithms / compilation technology / random access / simulation / von Neumann processors / typical algorithm / 60 / 000 gates/chip / /
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R. W. Hartenstein, K. Schmidt, H. Reinig, M. Weber: A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; in Will Moore, Wayne Luk (ed.): FPGAs; Oxford 1991 International Workshop on Fie