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Field-programmable gate array / Monte Carlo methods in finance / Parallel computing / Logic simulation / Monte Carlo method / Accelerator / Simulation / Hardware description language / Digital electronics / Electronic engineering / Logic design


Paper formatting guidelines for FPL 2005 proceedings
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Document Date: 2008-04-02 15:55:41

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File Size: 943,26 KB

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City

Schaumburg / /

Company

Nathan A. Woods XtremeData Inc. / Intel Memory / Altera / GPU / XtremeData White Paper XtremeData Inc. / Intel / XtremeData Inc. / /

Country

United States / /

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Facility

Plaza Drive / bridge FPGA / /

IndustryTerm

x86 processor / closed form solution / finance / multi-core processor / persistent interface chip / multi-core x86 processor / energy / /

Organization

MC Simulation Unit / /

Position

erT / candidate for hardware acceleration / rT / Controller / /

Product

XtremeData FPGA ISA module / MC / Quartus II v7.2 software / Quartus II v7.2 / XtremeData FPGA ISA / /

ProgrammingLanguage

C / /

ProvinceOrState

Illinois / /

Technology

dual processor / FPGA / Xeon processor / persistent interface chip / x86 processor / heat transfer / simulation / SRAM / DSP / VHDL / Mersenne Twister algorithm / /

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