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Applied mathematics / Logic in computer science / NP-complete problems / Formal methods / Boolean algebra / Boolean satisfiability problem / Field-programmable gate array / Conjunctive normal form / Routing / Theoretical computer science / Electronic engineering / Electronic design automation


Board-Level Multiterminal Net Assignment Xiaoyu Song1, William N. N. Hung2, Alan Mishchenko1, Malgorzata Chrzanowska-Jeske1, Alan Coppola3 and Andrew Kennings4 1 Department of ECE, Portland State University, Portland, O
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Document Date: 2002-03-01 13:11:46

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Satisfiability / Monterey / Hillsboro / Beaverton / Las Vegas / Berlin / Norwell / Waterloo / San Jose / /

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Multi-FPGA Systems / Programmable-Device Based Computing Systems / USA 3 Cypress Semiconductor / USA 2 Intel Corporation / Si / Chaff / Huge Logic Emulation Systems / /

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United States / /

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terminal BLRP / Portland State University / Terminal Net Routing / University of Waterloo / O port / /

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Department of ECE / University of Waterloo / ASIC / Portland State University / Portland / /

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Rob A. Rutenbar / W. Mak / D. Brasen / G. Saucier / M. Slimane-Kadi / Max Ave Vars Clauses Literals / Fadi Aloul / Joon Nam / Karem A. Sakallah / Gi-Joon Nam / /

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first author / designer / /

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Pentax K-x Digital Camera / /

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Saskatchewan / Nevada / Oregon / California / Ontario / /

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design verification / FPGA / FPGA chip / programmable interconnect chip / performance-driven routing algorithm / identical FPGA chips / solver algorithms / time algorithm / FPGA system / optimization algorithm / same chip / polynomial algorithm / nets connecting chip / ASIC / 2 chip / 1 chip / flow-based algorithm / simulation / separate FPGA chip / 3 chip / given chip / FPGA chips / CAD / /

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