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Digital electronics / Integrated circuits / Electronic design / Field-programmable gate array / Xilinx / Logic synthesis / Application-specific integrated circuit / Placement / Static timing analysis / Electronic engineering / Electronics / Electronic design automation


SmartOpt: An Industrial Strength Framework for Logic Synthesis Stephen Jang, Dennis Wu, Mark Jarvin Billy Chan, Kevin Chung Xilinx Inc. {sjang,wudenni,mjarvin,billy,kevinc}@xilinx.com
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Document Date: 2008-12-17 22:28:43


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File Size: 226,28 KB

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General Terms Alan Mishchenko Robert Brayton University of California / /

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tool chain / industrial tools / logic networks / technology mapping / static timing analysis tool / synthesis tool / recent academic synthesis tools / synthesis algorithms / synthesis tools / /

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set 20 / /

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ABC / /

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UC Berkeley / US Federal Reserve / University of California / Berkeley / /

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Stephen Jang / Mark Jarvin Billy Chan / David Nguyen Van Mau / Yassine Rjimati / Dennis Wu / Alan Mishchenko Robert / /

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hb / representative / /

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ABC / /

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FPGA / synthesis algorithms / simulation / Integrated Circuits / pdf / FPGA technology / CAD / /

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