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![]() | Document Date: 2008-02-01 13:16:46Open Document File Size: 60,91 KBShare Result on FacebookCitySan Francisco / Los Alamitos / Napa / /CompanySUBU / ADDU / AND / OR / SRL / Philips Semiconductors / Featuring Philips CPLDs Bernardo Kastrup Philips Research Laboratories / IEEE/ACM Intl / Morgan Kaufmann Publishers Inc. / /CountryNetherlands / /CurrencyUSD / / /EventForce Majeure / /FacilityPrentice Hall / / /IndustryTermconfigurable computing world / media processor / reprogrammable hardware / cascaded chain / related software tools / compilation chain / existing commercial products / hardware synthesis tool / software image / simplified software architecture / hybrid reconfigurable processor / /OrganizationASIC / Chimaera Reconfigurable Functional Unit / US Federal Reserve / From Assembly / /PersonRoss Morley / Paul Gorissen / Holstlaan / Menno Treffers / Jan Hoogerbrugge / Joachim Trescher / / /Positiontranslator / simple and straight forward / automatic translator / rt / XPLA Designer / programmer / /ProductFranklin / /ProgrammingLanguageHardware Description Language / /ProvinceOrStateNew Jersey / California / /PublishedMediumScientific American / /TechnologyFPGA / FPGA Processor / ASIC / VLIW media processor / MIPS processor / hybrid reconfigurable processor / simulation / SRAM / FZPTM technology / RISC processors / /URLhttp /SocialTag |