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Central processing unit / Parallel computing / Microprocessors / Instruction set architectures / Field-programmable gate array / MIPS architecture / Complex programmable logic device / Reduced instruction set computing / Hardware description language / Electronic engineering / Computer architecture / Electronics


Document Date: 2008-02-01 13:16:46

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City

San Francisco / Los Alamitos / Napa / /

Company

SUBU / ADDU / AND / OR / SRL / Philips Semiconductors / Featuring Philips CPLDs Bernardo Kastrup Philips Research Laboratories / IEEE/ACM Intl / Morgan Kaufmann Publishers Inc. / /

Country

Netherlands / /

Currency

USD / /

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Event

Force Majeure / /

Facility

Prentice Hall / /

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IndustryTerm

configurable computing world / media processor / reprogrammable hardware / cascaded chain / related software tools / compilation chain / existing commercial products / hardware synthesis tool / software image / simplified software architecture / hybrid reconfigurable processor / /

Organization

ASIC / Chimaera Reconfigurable Functional Unit / US Federal Reserve / From Assembly / /

Person

Ross Morley / Paul Gorissen / Holstlaan / Menno Treffers / Jan Hoogerbrugge / Joachim Trescher / /

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Position

translator / simple and straight forward / automatic translator / rt / XPLA Designer / programmer / /

Product

Franklin / /

ProgrammingLanguage

Hardware Description Language / /

ProvinceOrState

New Jersey / California / /

PublishedMedium

Scientific American / /

Technology

FPGA / FPGA Processor / ASIC / VLIW media processor / MIPS processor / hybrid reconfigurable processor / simulation / SRAM / FZPTM technology / RISC processors / /

URL

http /

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