Reducing the Barriers to Writing Verified Specifications Todd W. Schiller Michael D. Ernst University of Washington

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Date: 2012-08-23 11:19:39 Theoretical computer science Formal methods Software engineering Computing Logic in computer science Java Modeling Language Postcondition Extended static checking Predicate transformer semantics ESC/Java Precondition KeY		Reducing the Barriers to Writing Verified Specifications Todd W. Schiller Michael D. Ernst University of Washington Add to Reading List Source URL: homes.cs.washington.edu Download Document from Source Website File Size: 1,08 MB Share Document on Facebook

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