| Document Date: 2013-09-24 10:35:57
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City Viewport / / Company AVC / BP / Philips Electronics N.V. / Vertex / INTERFACE / North American Philips Corporation / VC1 / Intel Corporation / / Country United States / / / Event FDA Phase / / Facility Pipeline Overview / Pipeline Stages / Pipeline Stage Overview / Pipeline Stage Input / Pipeline State Overview / Media Pipeline / / IndustryTerm life sustaining applications / changes to specifications and product / communications bus/protocol / bus/protocol / / Organization Thread Spawner Unit / Transform-Domain Residue Unit / Video Front End Unit / VF Unit / 3DPRIMITIVE Command / Input Assembly / Primitive Assembly / / Person Purpose Pipeline / / Position author / Q45 Express Chipset Graphics Controller / Guard / Series Express Chipset Family Programmer / General / Multi-Context Scheduler / / Product I2C / / Technology Alpha / MPEG-2 / two-wire communications bus/protocol / Caching / RANDOM Access / / URL www.intellinuxgraphics.org / /
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G45: Volume 2: 3D/Media Intel® 965 Express Chipset Family and Intel® G35, G41, G43, G45, G54, Q43, Q45 Express Chipset Graphics Controller, and Intel® Series Express Chipset Family