| Document Date: 2005-08-08 21:58:24
Open Document File Size: 74,43 KBShare Result on Facebook
City Santa Clara / Austin / Context / Sunnyvale / Cambridge / Waltham / / Company IBM / AT&T / UNUM / TS702 Advanced Communication / Motorola Corporation / VIRATA Ltd. / AMD / IEEE Journal / Z. Onufryk AT&T Labs / Advanced Micro Devices / Multi-Channel DMA / / Country United Kingdom / / Event FDA Phase / / Facility Priority CPU Pipeline / CPU pipeline / RISC pipeline / UNUM pipeline / OPB Macro Library / / IndustryTerm communications processor design / large buffers on-chip / normal processor / communications functionality / interface specific processing / performance processors / interface specific hardware / aligned fixed width memory device / communications processor families / required on-chip / communications processor cost / software uses / workstation processors / fly-by processing / memory systems / system-on-a-chip / considerable processing power / this in custom hardware / software development / input processing / buffer management / control block processor / broadband access networks / Internet applications / broadband access equipment / event processing / programmable processor / communications tasks / on-board processors / purpose processors / communications processor / overhead event processing / communications processors / consumer applications / consumer devices / channel customization interface specific processing / networked consumer devices / software executing / Internet appliances / on-chip / application processing / output processing / packet telephony / / OperatingSystem VxWorks / BSD / / Organization Internal Bus Interface Unit / Event Processing Performing / VMP Network Adaptor Board / Based Communications Processor Since / / Person C.A. Thekkath / Figure / A. Basu / V / CID PC / / Position Mbps PCI Ethernet Controller / context scheduler / channel DMA controller / complex DMA controller / DMA controller / Controller Data Book / Controller / multi-channel DMA controller / T.D. / / Product CPU / AAL5 / / ProvinceOrState New Jersey / / Technology dedicated processor / RAM / typical RISC processor / workstation processors / on-board processors / designing communications processors / 200 MHz MIPS processor / V.34 / VxWorks / minimizing on-chip / ADSL / system-on-a-chip / ATM / second processor / operating system / Typical Embedded Processor Interrupt Performance processors / Select Logic DMA State Machine On-Chip / Operating Systems / performance processors / broadband access / Implementing Network Protocols / required on-chip / NetSilicon Net+ARM processor / encryption / Ethernet / large buffers on-chip / one processor / SPARC processor / programmable processor / separate control block processor / ARM processors / System-On-Chip / Virata Helium processor / communications processors / two ARM processors / SOC communications processors / purpose processors / communications processor / caching / SDRAM / Simulation / RTOS / DSP / Euphony processor / virtual circuit / cable modems / /
SocialTag |
Architectural Considerations for CPU and Network Interface Integration C. D. Cranor, R. Gopalakrishnan, P. Z. Onufryk AT&T Labs - Research Florham Park, NJ 07932, USA