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Computing / Channel I/O / Bus / Cache / Interrupt / Cell / Direct memory access / Computer hardware / Computer architecture / Motherboard


Architectural Considerations for CPU and Network Interface Integration C.D. Cranor, R. Gopalakrishnan, P. Z. Onufryk AT&T Labs - Research Florham Park, NJ
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Document Date: 2005-08-08 21:58:24

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File Size: 106,90 KB

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Company

AMD / Motorola / Intel / UNUM / Z. Onufryk AT&T Labs / /

Currency

SAR / /

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Facility

Full duplex / CPU pipeline / /

IndustryTerm

event processing / software environment / Internet appliances TDM Bus Intf / access devices / speed packet processors / data movement instructions / consumer devices / workstation processors / fly-by processing / application processing / packet telephony / /

Organization

PC/Priority Data Movement / UNUM Data Movement / /

Position

CPU Event Mapper External Events PC Context Scheduler / DMA controller / Tightly integrated memory controller / Ethernet controller / multi-channel DMA controller / /

ProgrammingLanguage

E / /

Technology

Encryption / Some processors / Flexibility Communications Processor / Ethernet / RAM / workstation processors / NIC Communications Processors / ATM / 2nd processor / SDRAM / Broadband access / DSL / High speed packet processors / /

SocialTag