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REPLAY
Results: 445

#	Item
211	Designing Hardware that Supports Cycle-Accurate Deterministic Replay Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-06-25 20:29:30 Computer buses Motherboard Central processing unit Digital electronics Microarchitecture Interrupt Front-side bus HyperTransport Itanium Computer hardware Computer architecture Electronic engineering
212	Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System ∗ Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-05-31 00:24:02 System software Central processing unit Application programming interfaces Thread Ring Kernel Interrupt handler System call Mach Computing Computer architecture Concurrent computing
213	The Officiating Replay System Hawk-Eye Coaching Technology Hawk-Eye Hawk-Eye is the world leader in sports officiating technology. HawkEye has an annual involvement in over 100 events including: The Wimbledon Championshi Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2012-12-12 11:11:11 Film techniques MIM-23 Hawk Camera angle Red Digital Cinema Camera Company Film Sports Cricket equipment Hawk-Eye
214	ILLINOIS QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs Intel: Gilles Pokam, Klaus Danne, Cristiano Pereira, Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-07-04 19:19:21 Pentium Intel Core P5 Front-side bus Xeon X86 Computer hardware Computer architecture Brands
215	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-03-10 10:28:34 Central processing unit Instruction set
216	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
217	Hawk-Eye Goal Line Technology How does it work? CAMERA TECHNOLOGY Hawk-Eye install 7 cameras per goal, the most common location is on the roof of the stadium, however there is a great Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2012-12-19 05:04:50 Goal-line technology Optical devices Camera High-speed camera Red Digital Cinema Camera Company Instant replay Sports Cricket equipment Hawk-Eye
218	do i:[removed][removed] Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-26 23:39:42 Central processing unit Parallel computing Chunk Process CPU cache Computer architecture Computing Computer hardware Computer memory
219	Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel T. King Gilles Pokam, Cristiano Pereira Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:28 Replay system Computer architecture Computing Parallel computing Thread
220	Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Nima Honarmand, Nathan Dautenhahn, Josep Torrellas and Samuel T. King (UIUC) Gilles Pokam and Cristiano Pereira (Intel) Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-03-29 16:27:21 P0 REPLAY Parallel computing

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