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Source code / Central processing unit / Instruction set architectures / Code generation / Compiler construction / Subroutine / Random test generator / Processor register / Functional verification / Computing / Software engineering / Computer programming


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Document Date: 2007-10-22 11:12:46

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File Size: 355,42 KB

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City

Moscow / /

Company

IBM / A. A. KRAVCHENKO A. S. / XArgs / RTL / SLL SRL / P. P. KOLTSOV N. V. / RAVEN Software / /

Country

Russia / Greece / /

/

Facility

I. S. KHISAMBEEV Scientific Research Institute / /

IndustryTerm

target processor / target device / software testing process / recent microprocessor systems / recent years technology / verification tools / universal systems / /

Organization

Russian Academy of Sciences / I. S. KHISAMBEEV Scientific Research Institute for System Studies / /

Person

GUI INTEG / Using Random / Brian R. Gaeke / /

/

Position

editor / Multiprocessor Cache Controller / VMIPS Programmer / visual template editor / /

ProgrammingLanguage

Verilog / /

Technology

Alpha / target processor / MIPS32 processors / Verilog / tested processor / paging / recent years technology / simulation / VHDL / 21164 CPU Chip / /

URL

http /

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