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Reduced instruction set computing
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1	Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2006-01-09 17:18:43 Computer architecture Computing Computer hardware Central processing unit Classes of computers Instruction set architectures Microprocessors Instruction pipelining Reduced instruction set computing Program counter Instruction set Processor design
2	Ratio Games Raj Jain Washington University in Saint Louis Saint Louis, MOThese slides are available on-line at: Add to Reading List Source URL: www.cs.wustl.edu Language: English - Date: 2008-11-05 11:12:44 Computer architecture Religion Instruction set architectures Computing Classes of computers Reduced instruction set computing Raj Jain RISC-V Jain St. Louis
3	eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:25 Computing Computer architecture Computer engineering Embedded microprocessors Instruction set architectures EnSilica ESi-RISC Central processing unit JTAG ARC 16-bit Reduced instruction set computing
4	Efficient Cryptography on RISC-V Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-11-30 11:00:03 Computer architecture Instruction set architectures Computing Reduced instruction set computing RISC-V Cryptography Cryptographic primitive Instruction set Institute for Applied Information Processing and Communications
5	RI5CY: User Manual May 2016 Revision 0.9 Andreas Traber () Michael Gautschi () Add to Reading List Source URL: www.pulp-platform.org Language: English - Date: 2016-05-25 19:13:33 Computer architecture Instruction set architectures Computing Computer engineering Central processing unit Instruction set Reduced instruction set computing Program counter MIPI Debug Architecture ARM architecture
6	ChapterIntroduction Add to Reading List Source URL: www.warthman.com Language: English - Date: 2003-03-07 17:54:29 Computer architecture Computing Computer engineering Instruction set architectures Power Architecture Classes of computers Central processing unit PowerPC Machine state register 64-bit computing Reduced instruction set computing Addressing mode
7	RISC-V Software Ecosystem Andrew Waterman UC Berkeley ! Tethered vs. Standalone Systems Add to Reading List Source URL: riscv.org Language: English - Date: 2016-04-09 11:41:57 Software Computer architecture System software Instruction set architectures RISC-V QEMU Reduced instruction set computing Kernel-based Virtual Machine Linux
8	MIPS Assembly Language Programmer’s Guide ASM-01-DOC Your comments on our products and publications Add to Reading List Source URL: www.tik.ee.ethz.ch Language: English - Date: 2009-09-02 12:08:50 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Assembly languages Programming language implementation Reduced instruction set computing IBM Basic assembly language and successors Processor register Instruction set Coprocessor
9	Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2016-02-24 05:00:01 Instruction set architectures Reduced instruction set computing RISC-V Instruction set ARM architecture Comparison of instruction set architectures
10	Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-03-03 11:01:50 Parallel computing Central processing unit Microprocessors Instruction set architectures Classes of computers Bit-level parallelism Reduced instruction set computing Instruction-level parallelism 64-bit computing Instruction set Very long instruction word Microarchitecture

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