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Central processing unit / Digital signal processing / Instruction set architectures / Assembly languages / Instruction set / ARM architecture / Digital signal processor / Reduced instruction set computing / Addressing mode / Computer architecture / Computing / Electronics


SOFLOPO: Towards Systematic Software Exploitation for Low-Power Designs
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Document Date: 2003-02-19 09:09:41

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File Size: 1.008,78 KB

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Company

Arithmetic / Logical / Motorola / Low Power Electronics / /

Country

Italy / Greece / /

Currency

USD / /

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Facility

University of Patras / Laboratory of Electromagnetics Electrical Engineering / PALACE RAPALLO/PORTOFINO COAST / /

IndustryTerm

basic processing / overall energy cost / energy costs / target processor / data processing instructions / similar processor / application-specific software / parallel processing capabilities / energy dissipation / energy cost / wireless multimedia protocol / consumed energy / target processors / digital signal processing core / energy consuming / electronics industry / digital communications / software execution / semiconductor chip / cellular applications / energy / /

Organization

Arithmetic and Logical / University of Patras / US Federal Reserve / Program Control Unit / Laboratory of Electromagnetics Electrical Engineering and Computer Technology Dept / Address Generation Unit / Data Arithmetic Logic Unit / /

Position

author / embedded system designer / /

Technology

dedicated processor / target processor / ADC / asl / ARM processor / DSP56156 DSP processor / RISC processor / semiconductor chip / 802.11 wireless multimedia protocol / ARM7TDMI RISC processor / JTAG / Two target processors / SRAM / simulation / DSP processor / DSP chips / DSP / -2 3 2 Processor / parallel processing / ARM7 processor / 3 Processor / cmp / /

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