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Instruction set architectures / ARM architecture / Computer memory / ARM9 / ARM7 / Direct memory access / CPU cache / Reduced instruction set computing / FreeBSD / Computer architecture / Computing / Computer hardware


Porting FreeBSD/arm to Marvell SoC Rafał Jaworowski [removed] BSDCan 2008, Ottawa
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Document Date: 2015-01-21 18:21:18

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Company

Acorn Computers Ltd. / ARM Ltd. / Orion BSDCan 2008 Generic System-On-Chip Memory / /

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Event

Force Majeure / /

Facility

PCIE bridge UART UART Porting FreeBSD/arm / /

OperatingSystem

FreeBSD / /

Organization

Harvard / /

Position

Memory controller / FLASH L1 D/I Cache Core CPU L2 Cache SRAM Local bus Interrupt controller / /

Technology

Ethernet / one chip / DSP / paging / System-On-Chip / FLASH / 2008 Generic System-On-Chip / SRAM / integrated circuit / UART / /

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