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Instruction set architectures / Classes of computers / Central processing unit / Parallel computing / Reduced instruction set computing / Complex instruction set computing / X86 / Superscalar / Instruction set / Computer architecture / Computing / Computer engineering


RISC vs. CISC – The Post-RISC Vasco Nuno Caio dos Santos Departamento de Informática, Universidade do Minho 4710 – 057 Braga, Portugal [removed]
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Document Date: 2002-01-26 10:53:05


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File Size: 1,99 MB

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Braga / Mac / /

Company

IBM / The Code Morphing Software / AMD / Transmeta / Cyrix / Intel / Microsoft / Apple / /

Country

Portugal / /

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Event

Man-Made Disaster / /

Facility

University of California Berkeley / Post-RISC Pipeline / /

IndustryTerm

3D software / portable devices / processors chips / simpler chip / owned software / computer software / software layer / software optimization / faster computer chips / instructions using hardware / /

OperatingSystem

Macintosh / /

Organization

University of California / Retire Unit / Universidade do Minho / Central Processing Unit / Michigan State University Department of Computer Science / /

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Position

programmer / /

Technology

Crusoe processor / simpler chip / actual RISC processors / Post-RISC processor / faster computer chips / Crusoe / CISC processors / generation Itanium processor / generic Post-RISC processor / operating system / Pentium chip / html / 106 ICCA’02 technology / RISC processors / VLIW processors / Post-RISC processors / processors chips / computer chips / 4 The Post-RISC Superscalar RISC processors / CISC chips / CISC chip / RISC chip / PowerPC chip / http / RISC chips / 486 chip / /

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