New York / Washington / DC / Delft / Bertinoro / Associativity / /
Company
IEEE Computer / Embedded Computer Systems / IEEE Computer Society Press / M. Reilly L. C. / Xilinx / Intel / /
Country
Netherlands / Italy / United States / /
Currency
pence / USD / / /
Facility
J. Hall / Dimitrios S. Nikolopoulos Institute of Computer Science Foundation / University of Crete / University of California / /
IndustryTerm
Software configuration / application specific coherence protocols / software-preconfigured communication activity / partitioned cache-scratchpad on-chip memory systems / software-managed partitions / energy advantages / software synthesis / Application-specific protocols / memory systems / media processing / communication management / software notification / multicore systems / energy / software initiation / all-to-all data exchanges on-chip / multicore processors / purpose systems / fit on-chip / mainstream computing environments / synchronization hardware / software platforms / aggressive non-blocking coherence protocols / software-managed memory hierarchies / on-chip / software configurable synchronization primitives / /
MarketIndex
FFT / STREAM / /
Organization
IEEE Computer Society Technical Committee on Computer Architecture / MIT / University of California / Berkeley / HiPEAC / ASIC / Dimitrios S. Nikolopoulos Institute / University of Crete / Computer Science Foundation for Research and Technology / Tags RDMA Command / European Commission / IEEE Computer Society / EECS Department / /
Person
S. Van Doren / Christos Sotiriou / I. Schoinas / Euriclis Kounalakis / Directly Cacheable Addressable (Scratchpad) / George Nikiforos / Manolis Katevenis / Saman P. Amarasinghe / K. Gharachorloo / K. E. Moore / Vassilis Papaefstathiou / Rodric M. Rabbah / J. R. Larus / Michal Karczmarek / David Maze / Stamatis Kavadias / Dimitris Nikolopoulos / William Thies / A. R. Lebeck / Xiaojun Yang / Michael I. Gordon / Jasper Lin / Alex Ramirez / S. K. Reinhardt / D. A. Wood / Georgi Gaydadjiev / Michael Ligerakis / George Kalokairinos / Spyros Lyberis / Dionisios Pnevmatikatos / Dimitris Tsaliagos / S. Steely / B. Falsafi / M. Sharma / Michail Zampetakis / /
Position
NI DDR Controller / editor / L2 controller / gr ABSTRACT General / DRAM controller / /
On-chip Communication and Synchronization Mechanisms with Cache-Integrated Network Interfaces Stamatis Kavadias, Manolis Katevenis ∗ Michail Zampetakis, Dimitrios S. Nikolopoulos Institute of Computer Science