Date: 2013-04-25 09:30:17Computer hardware Computer memory Instruction set architectures Parallel computing CPU cache Kernel Instruction set Thread Chunking Computer architecture Computing Central processing unit | | QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs∗ Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin GottschlichAdd to Reading ListSource URL: iacoma.cs.uiuc.eduDownload Document from Source Website File Size: 408,12 KBShare Document on Facebook
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