| Document Date: 2013-04-25 09:30:17
Open Document File Size: 408,12 KBShare Result on Facebook
City Tel Aviv / / Company QuickRec Hardware / Capo3 SYSTEM SOFTWARE / RTL / Josep Torrellas Intel Corporation / Intel / / Country Israel / / Currency pence / USD / / Event FDA Phase / / Facility University of Illinois / Branch Trace Store / MRR L2$ L1$ FPGA FPGA Bridge Bridge / Bridge FPGA / / IndustryTerm software system / software stack / software effects / mainstream processors / system software uses / inter-thread communications / privileged software / analysis tools / coherence protocol / hardware/software interface / hardware device / realistic cache coherence hardware / software architecture / system software / software-based simulators / multicore systems / / MarketIndex Chunk Memory / / NaturalFeature input OCEAN / chunk OCEAN / only OCEAN / combined OCEAN / / OperatingSystem SUSE Linux / Linux / / Organization RSW IAV / University of Illinois / US Federal Reserve / Illinois-Intel Parallelism Center / / Person Rolf Kassa / Klaus Danne / Tim Kranich / Cristiano Pereira / Stream Architectures (Multiprocessors) / Nima Honarmand / Gilles Pokam / Justin Gottschlich Nima / Nathan Dautenhahn / / Position Driver / private / WB / General / WB / Memory Controller / Replay Sphere Manager / Manager Processor Core Cache / / Product a software system called Capo3 / Capo3 / Simics / L2 / / ProvinceOrState Illinois / Iowa / / Technology FPGA / MESI coherence protocol / IA processors / 4 5 Replay Sphere Manager Processor / E5-2670 processor / time processors / Linux / default DEFLATE algorithm / 2.1 QuickIA Processor / 2.6 GHz E5-2670 processors / proposed algorithms / operating system / Shared Memory / mainstream processors / /
SocialTag |
QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs∗ Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Gottschlich