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Computer architecture / Computing / Computer hardware / Computer memory / Opteron / Cell / Multi-core processor / Intel Core / SPARC T5 / Advanced Micro Devices / Xeon / CPU cache


Optimization of a Lattice Boltzmann Computation on State-of-the-Art Multicore Platforms Samuel Williams∗,a,b , Jonathan Cartera , Leonid Olikera , John Shalfa , Katherine Yelicka,b a CRD/NERSC, b CS
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Document Date: 2012-09-06 23:48:36

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File Size: 1,07 MB

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