Back to Results
First PageMeta Content
Digital electronics / Diagrams / Logic in computer science / And-inverter graph / Retiming / Logic synthesis / Formal verification / Combinational logic / Standard cell / Electronic engineering / Electronic design automation / Formal methods


Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS
Add to Reading List

Document Date: 2006-05-01 19:34:23

Open Document

File Size: 173,20 KB

Share Result on Facebook
UPDATE