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Computing / Data / Software transactional memory / Rock / Non-blocking algorithm / CPU cache / Transactional memory / Parallel computing / Linearizability / Concurrency control / Transaction processing / Data management


Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory∗ Zhaoguo Wang†, Hao Qian‡, Haibo Chen‡, Jinyang Li§ † School of Computer Science, Fudan University ‡ Institute of Parallel a
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Document Date: 2013-07-16 15:24:14

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