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Company Checkpoint / IBM / Fujitsu / Fault-Tolerant Computing Systems / Swich / IEEE CS Press / Sequoia Hardware / IEEE MICRO Hardware / Xilinx / using Swich / / Currency USD / / Event FDA Phase / / Facility IMMEDIATELY AFTER A CHECKPOINT / Radu Teodorescu Jun Nakano Josep Torrellas University of Illinois / checkpoint Cache / Building Fault-Tolerant Scalable Shared Memory Multiprocessors / / IndustryTerm computation-intensive applications / slower hardware / graphs hardware / out-of-order processors / Speculative line management / out-of-order processor / cache replacement algorithm / cross-compilation tool chain / cache coherence protocol / simpler algorithm / memory hardware / in modern processors / / MarketIndex LARGE MINIMUM AND / / MusicAlbum I/O / / OperatingSystem Unix / Linux / Microsoft Windows / / Organization University of Illinois / IEEE Computer Society / / Person Min Ckpt Ckpt Ckpt Ckpt / Min Rollback / Urbana-Champaign / / / Position cache controller / synthesizable SDRAM controller / synthesizable SDRAM controller / and PCI and Ethernet interfaces / special directory controller / controller / / Product Leon2 / Checkpointing / Sparc64 processor / FPGAs / Sparc64 / Cache-Only Memory Architecture / / ProvinceOrState Illinois / / TVStation Kbit / / Technology FPGA / RAM / Linux / Unix / cache replacement algorithm / out-of-order processors / Cache Memory / SRAM / operating system / Sparc64 processor / Shared Memory / cache coherence protocol / VHDL / Ethernet / target FPGA chip / out-of-order processor / simpler algorithm / SDRAM / prototype The processor / S/390 G5 processor / / URL http / SocialTag 
SWICH: A PROTOTYPE FOR EFFICIENT CACHE-LEVEL CHECKPOINTING AND ROLLBACK EXISTING CACHE-LEVEL CHECKPOINTING SCHEMES DO NOT CONTINUOUSLY SUPPORT A LARGE ROLLBACK WINDOW. IMMEDIATELY AFTER A CHECKPOINT, THE NUMBER OF INSTRU