ISAOpt bar / Best Compiled Cache bar / Blocking bar / Third-Level Network Port / Na¨ıve Cache Parallelization bar / Oregon University of Illinois / TrigOpt bar / Base SAR bar / CompilerOpt bar / /
IndustryTerm
Extreme-scale systems / energy-efficient voltage/frequency / energy scaling / network energy / pruned tree network / memory system energy / energy/bandwidth trade-offs / multi-block chip / energy goals / synthetic aperture radar algorithm / active memory energy / Memory energy / lowest message energy / hierarchical on-chip network / cache-based algorithm / barrier/reduction network / hybrid tree networks / fat tree network / hierarchical networks / energy / target applications / energy-optimized interface / message energy decreases / 6x more energy / energy consumption / computation energy / firstlevel networks / power management / extreme-scale computer systems / user applications / energy-efficient manner / decision to use software / energy estimates / clock management / extreme-scale applications / Fat tree networks / energy efficiencies / less energy / energy efficiency / technology trends / multi-chip systems / test chip / computation energy scales / energy distribution / switch energy / communication energy / larger systems / minimum possible energy / barrier hardware / on-chip network / extreme-scale memory systems / barrier networks / Tree-based networks / message energy increases / similar message energy / challenge applications / energy minima / coherence protocol / leakage energy / 22nm technology / system in which hardware / processor chip / on-chip networks / energy costs / dataflow processors / technology scaling trends / energy-efficiency / energy cost / energy trends / fabrication technology / hybrid tree network / tree networks / runtime systems / message energy / computing systems / energy curves / energy-optimized network / low-energy communication / on-chip / sub-optimal energy / fabrication technologies / /