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Cache coherency / CPU cache / Cache / Dynamic random-access memory / Memory hierarchy / Controller / Bus sniffing / Scalable Coherent Interface / Computing / Computer hardware / Computer memory


HIERARCHICAL DIRECTORY CONTROLLERS IN THE NUMACHINE MULTIPROCESSOR by Alexander Grbic
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Document Date: 1999-09-21 22:20:44

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File Size: 4,01 MB

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Company

Cache Coherence Solutions / /

Facility

Computer Engineering University of Toronto Copyright / Computer Engineering University / /

IndustryTerm

implementations using custom hardware / software mechanisms / coherence protocol / field-programmable devices / Software-based approaches / /

Organization

Applied Science Graduate Department of Electrical / Electrical and Computer Engineering University of Toronto Copyright / Organization of Modules / Department of Electrical / Electrical and Computer Engineering University of Toronto Abstract In / /

Person

Alexander Grbic Hierarchical Directory Controllers / S. Srbljic / Alexander Grbic / Derek DeVries / Greg Steffan / Dan Vranesic / Guy Lemieux / Steve Caranci / Gordana / Robin Grindley / Rob Ho / Z. G. Vranesic / Kelvin Loveless / /

Position

memory Directory Controller / Network Interface Controller / Memory Controller / Directory Controller / controller / S3.mp / Memory Card Controller / /

Technology

coherence protocol / caching / simulation / SRAM / 83 Processor / FLASH / 111 Processor / NUMAchine Communication Protocols / /

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