Instantiation and Pretending to be an SMT Solver with VAMPIRE ∗ Giles Reger1 , Martin Suda2 , and Andrei Voronkov1,3,4 1 3

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Date: 2017-09-02 14:08:49 Theoretical computer science Mathematical logic Logic Automated theorem proving Logic in computer science Formal methods Logic programming Predicate logic Satisfiability modulo theories Unification Solver Resolution		Instantiation and Pretending to be an SMT Solver with VAMPIRE ∗ Giles Reger1 , Martin Suda2 , and Andrei Voronkov1,3,4 1 3 Add to Reading List Source URL: smt-workshop.cs.uiowa.edu Download Document from Source Website File Size: 267,38 KB Share Document on Facebook

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