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Central processing unit / Instruction set architectures / Branch predictor / Counter / Linear feedback shift register / CPU cache / Hardware performance counter / DEC Alpha / ARM architecture / Computer architecture / Computer hardware / Computing


Probabilistic Counter Updates for Predictor Hysteresis and Stratification Nicholas Riley Craig Zilles Department of Computer Science
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Document Date: 2005-11-03 16:47:01


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Computer Science University of Illinois / Non-Forwarding Store / /

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on-line aggregation / e-gskew / cache coherence protocol / superscalar processor / large-window processors / /

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University of Illinois / Predictor Hysteresis and Stratification Nicholas Riley Craig Zilles Department / US Federal Reserve / /

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Nicholas Riley Craig Zilles / /

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get_heap_head / LoC-based scheduler / /

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X8 / /

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Manitoba / /

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Alpha / perl / large-window processors / simulation / cache coherence protocol / /

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