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Standard cell / Signoff / SPICE / Verilog / Electronic circuit simulation / Synopsys / Signal integrity / Simucad / Electronic engineering / Electronic design automation / Digital electronics
Date: 2014-11-07 14:32:38
Standard cell
Signoff
SPICE
Verilog
Electronic circuit simulation
Synopsys
Signal integrity
Simucad
Electronic engineering
Electronic design automation
Digital electronics

Datasheet SiliconSmart Comprehensive Cell, I/O and Memory Characterization Overview

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Source URL: www.synopsys.com

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