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| Document Date: 2014-07-19 19:25:26 Open Document File Size: 2,40 MBShare Result on Facebook
Company RTL / IBM / Network Directory DirectoryCache Cache Memory MemoryController / / Facility Pipeline Switch Arbitration Inport / / IndustryTerm virtual networks / on-chip network / coherence protocol / notification network / / Organization MIT / / Person Sunghyun / Tushar Krishna / Owen Chen / Woo-Cheol / Woo Cheol / Bhavya / Woo Cheol Kwon / John Arends / Brett Wilkerson / / Position Private / Memory controller / coherence Dual channel DDR2 memory controller / controller / interconnect Memory controller / / RadioStation 35 Core / Core 1 / Core / / Technology FPGA / Cache Memory / Board Design / MIT MOSI coherence protocol / Shared Memory / /
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