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Central processing unit / Cache / CPU cache / Computer memory / Microarchitecture / AMD 10h / Parallel computing / LEON / Speculative execution / Computer hardware / Computer architecture / Computer engineering


The Design Complexity of Program Undo Support in a General-Purpose Processor Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu
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Document Date: 2005-10-16 18:49:08

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File Size: 161,70 KB

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City

Austin / /

Company

Checkpoint / RTL / ACM Press / Xilinx / /

Facility

port RAM / Computer Science University of Illinois / port RAMs / /

IndustryTerm

parallel applications / software reliability / software bugs / system-on-a-chip infrastructure / /

OperatingSystem

Linux / /

Organization

University of Illinois / General-Purpose Processor Radu Teodorescu and Josep Torrellas Department / IEEE Computer Society / /

Position

cache controller / synthesizable SDRAM controller / write-back cache controller / synthesizable SDRAM controller / PCI and Ethernet interfaces / back cache controller / controller / /

Product

LEON2 / LEON2 Processor / /

ProgrammingLanguage

L / R / K / /

ProvinceOrState

Texas / Illinois / /

PublishedMedium

IEEE Transactions on Computers / /

TVStation

Kbit / /

Technology

FPGA / Ethernet / RAM / target FPGA chip / Linux / modified processor / Virtex-II FPGA chip / system-on-a-chip / Multiscalar Processors / SDRAM / SRAM / LEON2 processor / Operating Systems / VHDL / FLASH / /

URL

www.pender.ch / www.snapgear.org / www.gaisler.com / http /

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