| Document Date: 2009-02-20 15:24:56
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Company IBM / SPEs / / / Facility Florida State University / Georgia Tech STI Center / / IndustryTerm recursive doubling algorithms / software tool / co-processors / Cell multiprocessor communication network / heterogeneous multi-core processor / slowest processor / heterogeneous multicore processor / / Organization National Science Foundation / Cell Center for Competence / Florida State University / Georgia Tech STI Center for Competence / / Person Sri Sathya Sai Baba / Min Mean Max / Ashok Srinivasan / / Position Memory Interface Controller / XDR memory controller / EIB data bus arbiter / memory controller / random walker / arbiter / / ProvinceOrState Florida / / Technology corresponding algorithm / two Cell processors / recursive doubling algorithms / eight co-processors / heterogeneous multicore processor / 0 1 2 3 4 5 6 7 8 Processor / Cell BE processor / two processors / Bruck algorithm / same processor / slowest processor / Cell processor / bandwidth Processor / / |
Optimizing Assignment of Threads to SPEs on the Cell BE Processor C.D. Sudheer, T. Nagaraju, and P.K. Baruah Dept. of Mathematics and Computer Science Sri Sathya Sai University Prashanthi Nilayam, India .