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Srinivas
Results: 235

#	Item
201	Locality-Aware Data Replication in the Last-Level Cache George Kurian, Srinivas Devadas Massachusetts Institute of Technology Cambridge, MA USA {gkurian, devadas}@csail.mit.edu Abstract Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-01-23 18:46:58 Computer memory CPU cache Central processing unit Cache algorithms MESI protocol Computer architecture Cache Computer hardware Computing
202	Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs Christopher W. Fletcher†∗, Ling Ren† , Xiangyao Yu† , Marten Van Dijk‡ , Omer Khan‡ , Srinivas D Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-01-23 18:47:27 CPU cache Dynamic random-access memory Synchronous dynamic random-access memory Side channel attack Microarchitecture DIMM CAS latency Static random-access memory SDRAM latency Computer memory Computer hardware Computing
203	IEEE COMPUTER ARCHITECTURE LETTERS Thread Migration Prediction for Distributed Shared Caches Keun Sup Shim∗ , Mieszko Lis∗ , Omer Khan‡ , Srinivas Devadas∗ ∗ Massachusetts Institute of Technology, Cambridge, M Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2012-10-06 13:39:24 Central processing unit Microprocessors Parallel computing Threads CPU cache Multithreading Multi-core processor Microarchitecture Cache Computer hardware Computing Computer architecture
204	Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia Lebedev, Srinivas Devadas Massachusetts Institute of Technology, Cambridge, Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-08-26 16:12:52 Parallel computing Computer memory Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Cache Memory coherence Computing Concurrent computing Computer hardware
205	Path ORAM: An Extremely Simple Oblivious RAM Protocol Emil Stefanov† , Marten van Dijk‡ , Elaine Shi∗ , Christopher Fletcher◦ , Ling Ren◦ , Xiangyao Yu◦ , Srinivas Devadas◦ † Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-09-14 19:02:00 Hash table Information science Database index Databases Oram
206	The Locality-Aware Adaptive Cache Coherence Protocol George Kurian Omer Khan Srinivas Devadas Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-04-22 20:43:35 Computer memory Central processing unit CPU cache Computer architecture MESI protocol Acumem SlowSpotter Bus sniffing Cache Computer hardware Computing
207	Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions G. Edward Suh, Charles W. O’Donnell, Ishan Sachdev, and Srinivas Devadas Computer Science and Artificial Intelligence Add to Reading List Source URL: csg.csail.mit.edu Language: English - Date: 2005-04-24 19:19:10 Central processing unit Physical Unclonable Function Randomness Trusted computing Parallel computing Ring Memory management unit Kernel Next-Generation Secure Computing Base Computing Computer architecture Computer hardware
208	1 Directoryless Shared Memory Architecture using Thread Migration and Remote Access Keun Sup Shim∗ , Mieszko Lis∗ , Omer Khan‡ and Srinivas Devadas∗ ∗ Massachusetts Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-05-09 15:17:07 Central processing unit Microprocessors Parallel computing Instruction set architectures CPU cache X86 Multithreading Multi-core processor Microarchitecture Computer architecture Computer hardware Computing
209	Java FX and Java SE 6 Update N Raghavan “Rags” N. Srinivas CTO, Technology Evangelism Sun Microsystems Inc. Add to Reading List Source URL: www.jfokus.se Language: English - Date: 2012-09-20 14:54:53 Cross-platform software Computing platforms JavaFX Java Sun Microsystems JavaFX Mobile Java version history Computing Java platform Java programming language
210	Deadlock-Free Fine-Grained Thread Migration Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan and Srinivas Devadas Massachusetts Institute of Technology Abstract—Several recent studies have proposed fine-grained, h Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2011-03-11 23:17:40 Parallel computing Concurrency control Microprocessors Central processing unit Threads Deadlock Multi-core processor Multithreading Lock Computing Concurrent computing Computer architecture

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