Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052

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Date: 2002-03-20 08:48:06 Computer hardware Computer memory Software pipelining AMD 10h Loop unwinding CPU cache Branch predication Explicitly parallel instruction computing Compiler optimizations Computing Computer architecture		Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052 Add to Reading List Source URL: research.ac.upc.edu Download Document from Source Website File Size: 80,68 KB Share Document on Facebook

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