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Superscalar
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#	Item
1	Superscalar programming 101 _parts 1-5_ Add to Reading List Source URL: www.quickthreadprogramming.com Language: English - Date: 2012-05-03 14:20:39 Computing Algebra Computer programming Parallel computing Multiplication Concurrent programming languages Numerical linear algebra Cilk Matrix Array programming OpenMP Array data structure
2	Contacts: Jim Ormond Add to Reading List Source URL: awards.acm.org Language: English - Date: 2016-05-18 11:44:53 Classes of computers Instruction set architectures Microprocessors Computer architecture Parallel computing EckertMauchly Award John Mauchly Complex instruction set computing Association for Computing Machinery Superscalar processor Computer X86
3	Security Analysis of x86 Processor Microcode Daming D. Chen Gail-Joon Ahn Arizona State University Add to Reading List Source URL: www.dcddcc.com Language: English - Date: 2016-08-05 04:38:17 Central processing unit Microcode Advanced Micro Devices X86-64 Instruction set Superscalar processor Microprocessor Microarchitecture X86 Micro-operation Firmware Intel Core
4	T9000 - superscalar transputer Richard Forsyth Bob Krysiak Roger Shepherd INrvl0S Limited - SGS-Thomson Microelectronics Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:50 Central processing unit Stack machines Microprocessors Parallel computing Transputer Computer architecture Processor register CPU cache IDL Instruction set
5	DOC Document Add to Reading List Source URL: www.capsl.udel.edu Language: English - Date: 2015-02-12 15:30:49 Parallel computing Guang Gao Computer architecture Software pipelining Symposium on Parallelism in Algorithms and Architectures Superscalar processor Dataflow architecture Instruction-level parallelism Data-intensive computing XPL Rock Josh Fisher
6	The Superblock: An Eective Technique for VLIW and Superscalar Compilation Wen-mei W. Hwu Nancy J. Warter Scott A. Mahlke Add to Reading List Source URL: web.eecs.umich.edu Language: English - Date: 2002-02-15 20:03:23
7	2013 IEEE Computer Society Annual Symposium on VLSI A Study on Polymorphing Superscalar Processor Dynamically to Improve Power Efficiency Keywords-Core Morphing; Asymmetric Multicore Processor (AMP); Add to Reading List Source URL: euler.ecs.umass.edu Language: English - Date: 2013-11-15 15:34:59
8	The finite state automaton based pipeline hazard recognizer and instruction scheduler in GCC Vladimir N. Makarov Red Hat Add to Reading List Source URL: gcc.cybermirror.org Language: English - Date: 2004-08-29 18:00:00 Central processing unit Classes of computers Parallel computing Models of computation Hazard Superscalar Instruction set Register renaming Reduced instruction set computing Computer architecture Computing Computer engineering
9	Runtime Aware Architectures Prof. Mateo Valero Director of BSC   Design of Superscalar Processors Add to Reading List Source URL: www.exascale.org Language: English - Date: 2015-01-29 07:24:49

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