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Superscalar
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#	Item
101	ADVANCED TECHNIQUES FOR IMPROVING PROCESSOR PERFORMANCE IN A SUPERSCALAR ARCHITECTURE Gordon B. STEVEN, University of Hertfordshire, Department of Computer Science, UK, E-mail: [removed] Lucian VINTAN, Adrian F Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:41:23 Computing Classes of computers Parallel computing CPU cache Cache Superscalar Microarchitecture Reduced instruction set computing Instruction-level parallelism Computer architecture Computer hardware Central processing unit
102	SIMULATING AN ADVANCED SUPERSCALAR ARCHITECTURE Adrian FLOREA, Lucian N. VINTAN, “Lucian Blaga” University of Sibiu, Computer Science Department, No. 4, E. Cioran Street, Sibiu-2400, ROMANIA, E-mail: aflorea@vectra. Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-01-29 12:15:29 Central processing unit Parallel computing Microprocessors Classes of computers CPU cache Superscalar Multithreading Breakpoint Benchmark Computing Computer architecture Computer hardware
103	060-computer-Geller[removed] Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2007-12-05 00:43:29 Central processing unit CPU cache Cache Computer memory Branch predictor Microarchitecture Parallel computing Superscalar Instruction-level parallelism Computer architecture Computer hardware Computer engineering
104	A VISUAL SIMULATION FRAMEWORK FOR SIMULTANEOUS MULTITHREADING ARCHITECTURES Adrian Florea1, Alexandru Ratiu1, Arpad Gellert1 and Lucian N. Vinţan1,2 1 Computer Engineering Department, “Lucian Blaga” University of S Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2011-07-24 18:09:27 Central processing unit Parallel computing Microprocessors Threads Superscalar Simultaneous multithreading Branch predictor Microarchitecture Multithreading Computer architecture Computing Computer hardware
105	DSP Architectures: Past, Present and Future* Edwin J. Tan, Wendi B. Heinzelman Department of Electrical and Computer Engineering Add to Reading List Source URL: www.ece.rochester.edu Language: English - Date: 2007-03-21 15:27:01 Digital signal processors Parallel computing Digital signal processing Instruction set architectures Texas Instruments TMS320 SuperH Very long instruction word Superscalar Microprocessor Computer architecture Computing Computer hardware
106	sku251528-001.qxd[removed] Add to Reading List Source URL: download.intel.com Language: English - Date: 2006-12-15 16:07:57 Microcontrollers Classes of computers Intel i960 Superscalar Microprocessor Reduced instruction set computing XScale Computer hardware Computing Electronic engineering
107	The Alpha[removed]Microprocessor Architecture R. E. Kessler, E. J. McLellan1, and D. A. Webb Compaq Computer Corporation Add to Reading List Source URL: h18004.www1.hp.com Language: English - Date: 1999-11-05 17:26:28 Central processing unit Alpha 21264 CPU cache Branch predictor Microarchitecture Register renaming Instruction pipeline Alpha 21164 Superscalar Computer architecture Computer hardware Computer engineering
108	Trace Cache Leon Gu Dipti Motiani Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2003-10-13 07:06:40 Central processing unit CPU cache Cache Computer memory Parallel computing Microarchitecture Branch predictor Superscalar Instruction-level parallelism Computer architecture Computer hardware Computing
109	VOL. 10, NO. 10 Architects Look to Processors of Future Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2001-09-20 16:39:08 Central processing unit Instruction set architectures Parallel computing Classes of computers Superscalar Reduced instruction set computing Very long instruction word Cell Microarchitecture Computer architecture Computing Computer hardware
110	The Design Space of Shelving Dezs Sima Institute of Informatics, Kandó Polytechnic Budapest, 19 Nagyszombat utca, 1034 Budapest, Add to Reading List Source URL: www.wlu.ca Language: English - Date: 2012-03-14 16:49:25 Parallel computing Shelving buffer Superscalar Register renaming Instruction window Central processing unit POWER1 R10000 Reservation stations Computer architecture Computing Computer engineering

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