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Superscalar
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#	Item
61	Software Logging under Speculative Parallelization ´ Garzar´an, Milos Prvulovicy , Jos´e Mar´ıa Llaber´ıaz , Mar´ıa Jesus ˜ V´ıctor Vinals, Lawrence Rauchwergerx , and Josep Torrellasy Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-09-30 19:59:18 Central processing unit Parallel computing Microprocessors Computer memory CPU cache Microarchitecture Cache Automatic parallelization Superscalar Computer hardware Computer architecture Computing
62	PACT’03 12th International Conference on Parallel Architectures and Compilation Techniques September 27 – October 1, 2003 Chateau Sonesta Hotel, New Orleans, LA Add to Reading List Source URL: www.ccs.neu.edu Language: English - Date: 2003-03-18 18:30:29 Instruction-level parallelism Superscalar Task parallelism Parallel computing Computing Very long instruction word
63	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation ˜ ´ Garzar´an, Milos Prvulovic, V´ıctor Vinals Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-29 23:57:21 Central processing unit Computer memory CPU cache Cache Parallel computing Hazard Superscalar Stack Computing Computer hardware Computer architecture
64	Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation∗ Jose Renau† James Tuck Wei Liu Luis Ceze Karin Strauss Josep Torrellas † Dept. of Computer Engineering, University of Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar Microarchitecture Speculative multithreading SPECint Coprocessor Computing Computer hardware Computer architecture
65	Energy-Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2002-07-31 19:49:18 Parallel computing Classes of computers Central processing unit Superscalar Branch predictor Reduced instruction set computing Instruction set Very long instruction word Microarchitecture Computer architecture Computing Computer hardware
66	POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure ∗ Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 17:56:00 Parallel computing Compiler optimizations Computer architecture Software optimization Profiling Profilers Automatic parallelization Superscalar Fortran Computing Computer programming Software engineering
67	866 IEEE TRANSACTIONS ON COMPUTERS, VOL. 48, Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-10-10 18:00:46 Central processing unit Microprocessors Parallel computing Threads Multithreading CPU cache Microarchitecture Superscalar IBM POWER Computing Computer architecture Computer hardware
68	Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-06-21 00:18:12 Computer architecture Parallel computing Computer memory Microprocessors CPU cache Cache Processor register Superscalar Multi-core processor Computing Computer hardware Central processing unit
69	HPL-PD Architecture Specification: Version 1.1 Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau Compiler and Architecture Research HPL[removed]R.1) February, 2000 (Revised) {kathail, schlansk, rau}@hpl.hp.com Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Central processing unit Parallel computing Classes of computers Explicitly parallel instruction computing Instruction-level parallelism Very long instruction word Instruction unit Superscalar Microarchitecture Computer architecture Computing Computer hardware
70	HARP-1 : A 120 MHz Superscalar PA-RISC Processor Kenji Matsubara, Takashi Hotta, Kenichi Ishibashi, Teruhisa Shimizu Hitachi, Ltd. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:45:47 Computing Computer architecture CPU cache Cache Reduced instruction set computing PA-8000 R8000 Computer hardware Central processing unit Computer memory

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