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VHDL / Altera / EDIF / Application-specific integrated circuit / Programmable logic device / Logic gate / Verilog / Synplicity / Altera Quartus / Electronic engineering / Hardware description languages / Logic synthesis


Document Date: 2003-01-08 23:21:54

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Company

Cadence / Synopsys / Mentor Graphics / Synplicity / HP / Altera Corporation / Viewlogic / /

Facility

Library Mapping Files / /

IndustryTerm

design processing / final product / waveform synthesis algorithms / software supports multiple device families / interfaces to tools / software processes / asychronous communications / verification tools / design entry tools / software runs / software interfaces / accessible on-line documentation / software supports multiple levels / programmable communications / digital signal processing / energy / /

OperatingSystem

Windows NT / Windows 95 / /

Organization

EDA / /

Person

Cadence Mentor Graphics Synopsys Viewlogic / /

Position

Symbol Editor / Graphic Editor / designer / appropriate editor for each design file / Text Editor / Floorplan Editor / Waveform Editor / Software Data Sheet The Waveform Editor / controller / Microperipheral library Programmable DMA controller / /

Product

MAX+PLUS II / /

ProgrammingLanguage

Verilog / Hardware Description Language / /

PublishedMedium

the LPM Quick Reference Guide / /

Technology

design verification / Verilog / Message Processor / simulation / waveform synthesis algorithms / AHDL / DSP / VHDL / UART / /

URL

http /

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